…and what I’ve learned could help in EMI reduction!
Executive Summary
Having multiple values of capacitors in parallel can inadvertently introduce resonances into a decoupling circuit. These can be mitigated by using a very small resistance in series with each capacitor. Even better, using multiples of the exact same capacitor can be far more effective than the same number of multiple value capacitors.
The effect of having parts far apart on a circuit board, introducing more inductance between them, could also require series resistance to dampen resonances, even if all capacitors are identical. Further, in the case of complex circuits with multiple parasitic impedances, varied capacitances might be appropriate, and series resistance might help to alleviate resonant effects.
These findings do not necessarily apply to non-ceramic capacitors, such as electrolytics or foil. Their equivalent circuits would have different parasitic component range values and should be analyzed for their own effects.
My Long Standing Practice
I’ve been using the parallel application of different ceramic capacitor values for over 30 years, with the intention of noise suppression and decoupling support across a broad range of frequencies. For instance, I’d put down a 10uF tantalum, 0.1uF ceramic (oops 100nF), 1nF and maybe even 100pF, in parallel, at the supply pin of a sensitive analog part. I would arrange the smallest capacitor to be closest to the part, then arrange them successively larger as they were placed successively further away. When impulses occur in the supply draw of the part, instantaneous support would come from the part with the smallest total inductance between the capacitive element and the pin, and that would be the smallest value part nearby. As that source ran out of juice, by that time the inductance to the next nearest part would have been overcome, and there was more support provided by that larger part. And so on. I just couldn’t understand why you wouldn’t do that.
Contrary Evidence
About 5 years ago, a colleague at Morningstar gave me a paper that claimed that it was a bad idea to do this. Being a scientific paper, it didn’t give an explanation in plain English, it went into some advanced derivation that lost me before the end of it abstract… or, something like that. I dismissed it. I kept saying, you have to be able to provide high quality support close to the pin.
Some time later, I realized that I could test the theory with the nanoVNA and real components on a VNA test board.
So I did, and the results were… surprising. Here’s a 100pF 1kV ceramic capacitor (such as we were using in 200V H-bridge stages to reduce EMI), on its own:
This plot has the same part and a second plot with a 1n0 1kV ceramic capacitor on top of each other:
Holy crap! Explain that bumpity-bump in the response away. I couldn’t.
Should We Care?
Yeah, we should. I mean, the world’s not going to come to an end with a peaky response curve in your decoupling network. However, wherever there’s a peak or an apparent discontinuity, we should be thinking two things:
- Why is it like that?
- What impact might it have when everything goes to… well, you know, doodle crap.
It turns out that noise comes at you from all sides, and at all wavelengths. Part of the job of the decoupling network is to suppress this noise. And, what happens when the noise comes in at a wavelength where the decoupling network is less effective / has a higher response on the plot? Well, rather than being suppressed, it gets through!
However, it’s even worse than that. A sharp peak in the response curve implies a resonance, and that’s a bigger problem. It’s kind of like a frequency funnel – it shepherds all of the incident frequencies and kind of pushes them toward the frequency of the peak. Yes that’s right, wherever the sharp peak is significantly above the background, it will bring in noise of all kinds, and kind of push it to the peak frequency. All of that tends to line up the noise in one place, and, well kind of amplifies the noise, rather than suppressing it.
Now, there are two things I need to point out here. It’s not actually amplifying the noise, there are no active elements. It just looks like it might be. What’s actually happening is that it’s gathering the energy in the region and, as much as it can depending on the noise sprectrum and source impedance etc, it will cause it to come out at the frequency of the peak. This is counter to our intention of noise reduction, can be detrimental to the operation of our circuit (e.g. an ADC measuring signals might give bogus results?), and as a foreshadow of later discussion, can cause emissions to bunch up at one frequency, making it show up higher on a spectrum analyzer, and causing an EMI failure.
This revelation to me was all yet to come, when I did those nanoVNA measurements years ago. Over my career, I’ve had issues with EMI, and sometimes it has been difficult to solve… but I think there’s a way to look at it which can help a lot. Maybe some day I’ll get the chance to prove it.
The Video that made Me Look Deeper
Several months ago, I stumbled onto this Youtube video. I resisted watching it for a while, maybe because I didn’t want to find out that I was wrong.
I flagged it as something that I had to watch, but for a few months, just didn’t seem to find the time. Then, a few weeks ago, I did find the time. Hmm… well, it was certainly food for thought!
Hans Rosenberg has a lot of interesting YouTube videos, a lot of great information. I’m not sure I agree with his viewpoint on everything – it’s all true, and watch for extenuating circumstances that change things subtlely.
So, what the F? (Farad)
It appears that the capacitive and inductive elements of one of the capacitors is interacting with the other capacitive and inductive elements in the circuit – here it’s the other decoupling capacitors, below it might be board inductance and parasitic capacitance in large wirewound inductors as well.
Simulation involves Much Less Soldering! And fewer burnt fingers…
I could not believe what I saw, so I coded up my own LTspice simulation to see what he was talking about. Here is the ASC simulation file and the PLT plot file.
How The Simulation is Set Up and Which Networks are Simulated
There are a bunch of various simulations happening all at once in the simiulation linked above. The stimulus is a swept signal from 1 MHz to 1 GHz, with the frequency displayed on the horizontal logarithmic scale. The vertical scale is in dB, so it’s logarithmic as well.
The series impedance into each tested network is 50 Ohms, and a 50 Ohm load on the output. The input would show as 0 dB, so the highest the output can be is -3 dB with the 50/50 divider.
Each “real” capacitor is represented by its series equivalent model of C, Ls, and Rs. These values were “borrowed” directly from the table shown in the video cited above, because I wanted to reproduce Hans’s results.
There are, at present, 18 different networks connected to the same source, each with its own output that can be displayed in the plot window. I suggest plotting mag(V(OutN), so you don’t get confused by the phase plots. The mag() function preserves the magnitude of the signal and sets the phase to zero, so all of the plots result in one superfluous horizontal phase line through the middle of the plot, which is more readily ignored.
Here is a table describing the 18 networks simulated:
| Seq | Signal | Condition |
|---|---|---|
| 1 | Out1 | 1 x 100nF capacitor equiv model |
| 2 | Out2 | 1 x 10nF capacitor equiv model |
| 3 | Out3 | 1 x 1nF capacitor equiv model |
| 4 | Out4 | 1 x 100pF capacitor equiv model |
| 5 | Out5 | 1 each of 100nF, 10nF, 1nF, 100pF capacitors equiv models |
| 6 | Out6 | 1 each of 100nF, 10nF, 1nF, 100pF capacitors equiv models, each one with approx 6xRs in series |
| 7 | Out7 | 1 each of 100nF, 10nF, 1nF, 100pF capacitors equiv models, each one with approx (10 to 11)xRs in series |
| 8 | Out8 | 4 x 100nF capacitor equiv model |
| 9 | Out9 | 4 x 100nF capacitor equiv model, each one with approx 11xRs in series |
| 10 | Out10 | 5 x 100nF capacitor equiv model, each one with approx 11xRs in series |
| 11 | Out11 | 6 x 100nF capacitor equiv model, each one with approx 11xRs in series |
| 12 | Out12 | 6 x 10nF capacitor equiv model, each one with approx 10xRs in series |
| 13 | Out13 | 6 x 1nF capacitor equiv model, each one with approx 11xRs in series |
| 14 | Out14 | 6 x 100nF capacitor equiv model with varied series inductances added |
| 15 | Out15 | 1 each of 100nF, 100pF capacitors equiv models |
| 16 | Out16 | 1 each of 100nF, 100pF capacitors equiv models, each one with approx 6xRs in series |
| 17 | Out17 | 2 each of 100nF capacitor equiv model, each one with approx 6xRs in series |
| 18 | Out18 | 6 x 100nF capacitor equiv model with varied series inductances added, each one with 11xRx in series |
Step 1: Confirmation of the Observation seen on my nanoVNA
Well, would you look at that. This comparison of Out1, Out2, Out3, Out4 and Out5, confirms what my nanoVNA measurement implied – see the bumpity-bumps in the response just below each capacitor’s self-resonant point? OK, let’s call them “resonance peaks”, because that’s what they are. They prove that with real-world values for C, Ls, and Rs, you can derive the result that I saw on the nanoVNA, and that Hans discussed in his video.
Step 2: Dampening the Resonant Peaks
This comparison of Out5, Out6 and Out7 demonstrates that putting a series resistance on each individual capacitor, the “peakiness” of the resonances can be reduced, getting back more to what I was hoping to do in the first place. Now, you can play with different values here, I sync’d them with the Rs of each capacitor, they were kind of hand tuned and I tried to make them values in the E12 standard values in a decade, just my little prejudice about numbers. What you can see is that the series resistance reduces the absolute effectiveness of the network – it’s higher now in the areas of self resonance, where it used to be the lowest – but also knocks down the resonant peaks accordingly. A higher series resistance make the network less effective and less pronounced resonant points.
Step 3: Comparison to a Bunch of Same Valued Capacitors
Here’s a comparison of Out7, Out8, Out9, Out10 and Out11. What you can see is that the least effective network was my hand-optimized widely varied different capacitance value network. Instead of 4 different values, 4 of the same value actually performed better – without series resistance of course, it had a very low response at its self resonant point. With series resistance, its response was much more smooth. Why would you want to do this? Well, it comes back to what Hans said in his video, and something I’ll look a bit into later, that the parts could affect each other similar to how the different valued parts affect each other, if they differ somewhat in equivalent model somehow – different manufacturers, different batches, or whatever.
In any case, then we look at more capacitors of the same value, 5 of them, and then 6 of them, each with the series resistance, and, as expected, 5 performs better than 4, 6 performs better than 5. But, surprise surprise, except at the very top of the range, all options seem to outperform the original 4 different value network, even with resistors to keep them from causing bad resonances.
Step 4: Comparison of a Bunch of Same Valued Capacitors, using Different Values
This comparison of Out11, Out12, and Out13 seems to show that a bunch of the higher value 100nF capacitors in parallel (again with series resistances) is better almost across the board than the lower value 10nF and 1nF capacitors in the same quantity. What is a bit surprising is that even at high frequencies, where the lower valued capacitor should be superior, the difference isn’t very dramatic. That’s probably because that it’s above the self-resonant frequency, where it’s not so much the capacitance but the inductance that is taking over the part’s frequency response.
Step 5: What Happens if there’s a lot of Board Impedance between the Capacitors?
When comparing Out8, Out11, Out14 and Out18, we see that if there’s substantial inductance between otherwise same-sized capacitors, they start to exhibit the “peakiness” of resonance, in spite of being the same value. Putting a resistance in series with each capacitor reduces the peakiness substantially, almost eliminating the resonances. The result is, the effectiveness of the network is reduced, but not as much as you might guess, given the effect without the resistances. Here, the series resistance combats a problem that we may not even know that we have.
Step 6: A Last Gasp at Trying Different Values Together
I just had to try this. What if the smaller capacitance is 3 decades smaller than the larger, would they be far apart enough to prevent the peakiness of resonance? Here we compare Out1, Out4, Out15, Out16, and Out17. The idea was that, as the 100nF capacitor poops out near 1 GHz, the 100pF capacitor might pick up the slack, without the interaction between them.
Alas, it didn’t help, there was a strong resonance. Putting a series resonance did help of course, it reduced the resonance, but its effectiveness is still surpassed by two 100nF capacitors in parallel, with the same series resistances, as before.
Could the Resistors be a PROBLEM?
Like, for dissipation? Because they don’t cause a significant problem with decoupling impedance, as above.
Well, let’s see. What frequency are we talking about that could have significant energy… maybe 40 kHz, with a 150 Vp-p waveform (say). The worst case current would be in the 100 nF capacitor. So at 40 kHz, Xc=40 Ohms, so the current could be 2.7 Arms (3.8 Ap-p). With a resistance of say 200 milliOhms, this resistor could dissipate 1.4W.
This power is substantial, but the number seems high. It’s best to recalculate for your own proposed design, and then try it to see what the dissipation might be.
What’s the Bottom Line?
This does not suddenly make me a decoupling / grounding / EMI expert… and what I’ve done strongly suggests that you should try multiple ceramic caps of the same value across EMI areas of concern first (like in your high power H-bridge circuits, hint hint).
If the board design places ceramic capacitors significantly far apart from each other on the PCB, consider putting the small series resistances in series with each, to ensure that they don’t resonate with all that parasitic inductance between them.
And for those circuits with a bunch of parasitic impedances that are going to be unknown and vary from unit to unit (power conversion with big switch FETs and power inductors on wire leads, say), it might still be appropriate to put down multiple values at different places, in case you need to compensate both for weird capacitances and inductances showing up where you don’t expect, and board distance impedances. If you do have multiple values, put a small series resistance in series with each one. I might suggest finding the actual specified internal series resistance Rs for each type of part, and use some small multiple of that value.
Other types of capacitors, such as electrolytics and film capacitors, may not exhibit these effects. Their equivalent circuits would have to be studied and tested to see if they suffer from the same effect. You especially would not want to put a series resistance on a large bulk storage capacitor (like on the output of your power conversion system), because the current flowing there will be very substantial, the power loss would be significant, and it could seriously degrade the bulk storage performance.